New analog front-end IP development targets up to 224Gb/s PAM4 optical I/O to improve bandwidth density and reduce power for AI interconnect.

Omni Design Technologies, Inc., a leading provider of Wideband Signal Processing™ solutions, today announced critical advancements in its ongoing development of a 200G-class Co-Packaged Optics (CPO) analog front-end (AFE) with advanced 3nm process, including a high-swing linear transmit (TX) driver and a low-noise receive (RX) transimpedance amplifier (TIA). The new CPO AFE IP is designed to address the growing power and bandwidth challenges faced industry-wide of moving data at 200G-class speeds for AI scale-up and scale-out connectivity in data centers.

Exploding bandwidth requirements in AI infrastructure are pushing the industry to place optical I/O closer to the switch/compute package in order to enable higher density and lower energy per bit. Omni Design’s CPO AFE products leveraging advanced 3nm process address this need by delivering the critical electrical-to-silicon photonics interface required for high-speed optical links.

“As AI training and inference fabrics grow, the industry is being forced to rethink power and bandwidth at every interface. Co-Packaged Optics is a critical architectural shift, with the analog front-end playing a key role in achieving system-level performance and efficiency,” said Kush Gulati, President and CEO of Omni Design Technologies. “This development continues to leverage our deep analog and mixed-signal expertise to help customers push optical I/O closer to the compute and switching silicon—improving bandwidth density while driving down power.”

These advancements expand Omni Design’s portfolio beyond ultra-high-speed data conversion, reinforcing the company’s leadership in enabling both optical and electrical interconnects for modern AI data centers.

Key Features and Benefits

• 224Gb/s PAM4 Support: High throughput to meet the bandwidth demands of AI scale-up and scale-out fabrics.
• Superior performance: Built-in programmable transfer functions to achieve robust link performance
• 3nm Process: Advanced manufacturing for maximum integration density and low power consumption.

Source: BUSINESS WIRE